Introduction
Many of us enjoy the convenience of vending machines. They provide us a snack on the go, and they are not difficult to use. Some vending machines come with keypads requiring us to type the address of the snack or drink that we desire, some come with large pushbuttons. Regardless, all vending machines operate basically the same way. We put in our money and make a selection, and then a treat pops out at the dispenser.
The main interactive 4–to–1 multiplexer at the top of this page is like a vending machine that sells four different treats: D0, D1, D2, and D3. For our analogy, the switches S0 and S1 would be the keys of the keypad that you use to select a treat. And Y would be the dispenser where the treats come out. Table 1 below shows the relationship between the selector switches and the four trains of merchandize. As an example, when you select S1S0 = 01 the D1 train lines up with the dispenser so that as long as you have money you can buy D1 treats. You get the idea.
| Data Train/Bus to Y |
S1 |
S0 |
| D0 |
0 |
0 |
| D1 |
0 |
1 |
| D2 |
1 |
0 |
| D3 |
1 |
1 |
Table 0: 4-to-1 Mux Truth Table
Universality of Multiplexers
At face value a multiplexer is a logic circuit whose function is to select one data line from among many. For this reason, many people refer to multiplexers as data selectors. We show the block diagram of a 4x1 multiplexer in Figure 1. The wedge shape of the symbol is not accidental. It is supposed to depict how the multiplexer funnels information from multiple lines to one line. But as in many things in life, the face value is only part of the story. With a little imagination, you can implement any Boolean function with multiplexers. But we are getting ahead of ourselves just a little bit. As a data selector, a multiplexer is still very useful. Registers and counters, for example, often depend on multiplexers to maintain data integrity. Specifically, a universal shift register employs multiplexers for mode selection. In such application each of the data lines represents one mode of operation.
Figure 1:
Block diagram of 4x1 multiplexer
Two examples follow by which we demonstrate the universality of multiplexers. Because this article is about the 4-to-1 multiplexer, we give examples that use it. For more examples, see the other multiplexer articles.
Three input XOR example
Table 1 below is the truth table of a three input XOR gate. The table is arranged such that X is the most significant bit and Z is the least significant bit. To implement the function using a single 4x1 mux, we begin by assigning the most significant bit in the table to the most significant selector switch: S1 = X. We do the same for
the next significant bit until there are no selector switches left: S0 = Y. Next, we treat Z as the data input to the multiplexer; so that X and Y will determine the relationship between Z and F. Here is the end result: when XY = 00, F = Z; when XY = 01, F = Z’; when XY = 10, F = Z’; when XY = 11, F = Z. Table 2 shows the XOR truth table as mapped to the multiplexer.
| X |
Y |
Z |
|
F |
| 0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
| 0 |
1 |
1 |
0 |
| 1 |
0 |
0 |
1 |
| 1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
| 1 |
1 |
1 |
1 |
Table 1: Three input XOR truth table
| S1 |
S0 |
DATA |
|
F |
| X |
Y |
Z |
F |
| 0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
| 0 |
1 |
1 |
0 |
| 1 |
0 |
0 |
1 |
| 1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
| 1 |
1 |
1 |
1 |
Table 2: XOR mapped to multiplexer
It is customary to assume that the signal Z is available in both true and complemented forms. Nonetheless, we show the inverter in our design in Figure 2.
Figure 2:
Mux as XOR gate
Three input majority function
As shown in Table 3 below, a majority function is a logic circuit whose output is true if more than 50% of the inputs are true. The output is false otherwise.
| X |
Y |
Z |
|
F |
| 0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
| 0 |
1 |
1 |
1 |
| 1 |
0 |
0 |
0 |
| 1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
| 1 |
1 |
1 |
1 |
Table 3: majority function truth table
There is no specific rule for choosing the most significant bit when building the truth table from the Boolean expression. However, once you build the table, the significance of the bits must coincide with the significance of the selector switches of the multiplexer. We show the mapping in Table 4.
| S1 |
S0 |
DATA |
|
F |
| X |
Y |
Z |
F |
| 0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
| 0 |
1 |
1 |
1 |
| 1 |
0 |
0 |
0 |
| 1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
| 1 |
1 |
1 |
1 |
Table 4: majority function mapped to multiplexer
From a multiplexer’s perspective, it is customary to show the relationship between the output F and the input data lines as a function of the selector switches. We do so in Table 5 below. Table 5 is really just a collapsed version of Table 4. In Table 4 each permutation of S1S0 is repeated twice (i.e. 00, 00; 01, 01; etc). Table 5 shows
each permutation once.
| S1 |
S0 |
|
F |
| X |
Y |
F |
| 0 |
0 |
0 |
| 0 |
1 |
Z |
1 |
0 |
Z |
| 1 |
1 |
1 |
Table 5: modified truth table
rom Table 5 (or Table 4) we can see that the value of F does not depend on Z when S1S0 = 00 or S1S0 = 11. Figure 3 below shows the circuit implementation of the majority function.
Figure 3:
majority circuit
Observation
The procedure we use to implement the two examples with the 4–to–1 multiplexer is straightforward. You can follow the same method to implement any three input function with a 4x1 mux. Indeed the general rule is true: you can implement any n input function with a multiplexer that has n–1 selector switches. The first n–1 inputs are assigned to the selector switches; the last input is treated as the source of data to the multiplexer.
