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The Gated D Latch Nand Base

The interactive Gated D Latch Nand Base digital logic circuit, with Boolean function and truth table.
Click on the board to energize the circuit.VHDL Program
Watch Short Film
TRUTH TABLE
Input Output Comment
CLK D Q not-Q
0 0 Latch Latch
0 1 Latch latch
1 0 0 1
1 1 1 0

INTRODUCTION

The particular design of the interactive Gated Data Latch shown above is implemented with four NAND gates. Because from a transistor perspective NAND gates are the most efficient gates with two or more inputs, this Gated D Latch is more cost effective than its cousins (e.g., The Data Latch R/S Base): it uses fewer transistors and fewer wires to accomplish the same task. Apart from efficacy, this Gated Data Latch is like all Gated Data Latches: it is capable of storing and operating on one bit of information. For this reason, in real applications, Gated Data Latches are often found in large groups such as shift registers and counters. Furthermore, because they are simple to use, Gated Data Latches are the preferred multivibrators in graduate design laboratories around the world and they are used to design elaborate machines.

The State Transition Table

Since in Boolean algebra each variable can have two possible values, 0 or 1, the circuit has two possible states (q = 0; q = 1) and four possible input conditions (CD = 00; CD = 01; CD = 10; CD = 11). And since the final state Q is a function of the inputs and of the initial state variable, we can create a table showing how Q changes based on the values of D, C and q. Such a table, Table 1, is shown below. We call the table a state transition table because it shows the final state Q as a function of the input conditions D and C and the initial state q.

Given state
q
Input Condition
CD=00 CD=01 CD=10 CD=11
0
1

Table 1: Empty State Transition Table

To fill the table we simple evaluate Q at the indicated values for CD and q. For example, at C = 1, D = 0, q = 1:

Q = D • C + q • C = 0 1 + 1 • 1 = 0 + 0 = 0.

Hence, we place Q = 0 in the appropriate cell, as shown in Table 2.

Given state
q
Input Condition
CD=00 CD=01 CD=10 CD=11
0
1 0

Table 2: State Transition Table

We complete the evaluation of Q and fill the state transition table as shown in Table 3. Feel free to check that our work is correct.

Given state
q
Input Condition
CD=00 CD=01 CD=10 CD=11
0 0 0 0 1
1 1 1 0 1

Table 3: State Transition Table

State Transition Diagram

Now that we have a complete state transition table, we can use the information to create a state transition diagram. A state transition diagram is a picture showing how the circuit moves from state to state. Figure 3 below shows our state transition diagram.

 Gated D Latch Nand base image

Figure 3

Stable and Unstable Transitions

At this point all that's left is to identify the stable and unstable transitions. In the state transition diagram, the arrows that point from one oval to another oval represent unstable transitions; the arrows that loop back represent stable states. In the table the unstable transitions are the cells where Q ≠ q. Table 4 below shows the unstable transitions in green.

Given state
q
Input Condition
CD=00 CD=01 CD=10 CD=11
0 0 0 0 1
1 1 1 0 1

Table 4: State Transition Table

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