INTRODUCTION TO THE MASTER-SLAVE DESIGN
The master-slave flipflop design demonstrates one of the most fundamental concepts in modern engineering: Defense in Depth. The basic idea behind the Defense in Depth design philosophy is that you never want to build a system that is vulnerable to a single failure. Accordingly, to minimize the risk associated with your design, you must take preemptive measures to reduce the probability of failure or to mitigate the consequence of failure. One of the simplest and most straightforward means of
accomplishing Defense in Depth is Redundancy for Reliability.
The master-slave flipflop is one such design that achieves system integrity through redundancy. Every master-slave flipflop comprises two latches and one inverter. The latches are arranged in such a way that the first latch, the master, drives the second latch, the slave. In addition, the inverter connects the clock/enable signal of one latch to the clock/enable signal of the other latch. Recall that the enable/clock signal serves as a key that opens a door: when the signal is asserted (equals to 1) the door
is open and other signals can enter, but when the signal is not asserted (equals to 0) the door is close and no other signal can enter. Therefore, the inverter effects that the door to the master and the door to the slave cannot be open at the same time; rather, when one door is open, the other must perforce be close.
This one door at a time technique turns out to be the backbone of the master-slave design: it minimizes the effect of erroneous inputs on the outputs of the circuit. When the clock signal is 1, causing the door to the master to be open, the output of the master latch is controlled by the input signals S and R. At the very same time, however, the door to the slave latch is close; thus, the slave latch is not affected by any change to the master. When the clock signal is 0, on the other hand, the door to the master is close and the door to the slave is open. At this time, the master latch can drive the slave latch: forcing the slave’s output to equal the master’s output.
This is a good place to go back to the circuit and try it out. While you are there, notice that the master-slave flipflop is congruent to the latch used to build it. In other words, the master-slave flipflop does exactly what the latch does – except the master-slave is more robust and thus more reliable in real machines.
ANALYSIS AND VERIFICATION
In analyzing the master-slave reset-set flipflop, we aim to expose enough details about the operation of the circuit so that ideally no further number crunching is necessary. Now of course we can never really assure everything. Still, we want to expose at least four aspects of the circuit: how many states the circuit has; how the circuit moves between states; which transitions are unstable; and, of course, the Boolean function that defines the behavior of the circuit. Much of the work involved in multivibrator
analysis problems is redundant: the task is to essentially present the same information over and over using different models, so as to emphasize different aspects of the circuit. On the bright side, because of the built-in redundancy, feedback sequential circuit analysis does not involve much thinking, once you know a good method.
The method we use goes like this: first get the Boolean function from the circuit; then from the Boolean function get the state transition table and the state diagram. From the state transition table, determine stability.
DERIVATION OF THE BOOLEAN/SWITCHING FUNCTION
Because the SR Master-Slave Flipflop is actually two Gated SR Latches connected in series, we can just use the Boolean function for the Gated SR Latch to get a switching expression for the SR Master-Slave Flipflop. As the expression for the Gated SR Latch is Q = S • C + R • q + C • q, we distinguish the master latch as Qm and the slave latch as Qs. In addition, we account for the NOT gate by inverting the Clock variable C of the slave latch.
Just to give you a heads up before we start playing around with the variables, an implicit assumption that we make through our simplification steps is that you understand not-Q is not the complement of Q. Two variables are complementary when they always take on opposite values. Such is not the case for Q and not-Q, as you can verify in the interactive circuit for the Gated/Clocked SR Latch when CSR = 111.
Now to the equations:
| Qm = S • C + R • qm + C • qm |
|
The master latch |
| Qs = Qm • C + not-Qm • qs + C • qs |
|
The slave latch |
Since not-Q
m= q
m 
(C
R), which simplifies to CR +
qm, we substitute for not-Q and get
| Qs= Qm • C + (CR +qm) • qs + C • qs |
|
|
| Qs= Qm • C + (C+ R) • qm • qs + C • qs |
|
after cancelling the double negatives. |
| Qs= Qm • C + C • qm • qs + R • qm • qs + C • qs |
|
after cancelling the double negatives. |
Here is how we simplified not-Q.
| not-Qm = qm (C R) |
|
|
| not-Qm = qm • (C • R) |
|
after rewrite each NAND as NOT-AND |
| not-Qm= qm + (C • R) |
|
after cancelling the double negatives |
| not-Qm= qm + C • R |
|
after cleaning out the parentheses |
At this point no further work is necessary concerning the Boolean function. So we proceed to drawing
the state transition table. Again, the Boolean expression for the SR Master-Slave Flipflop is
| Qm = S • C + R • qm + C • qm |
|
The master latch |
| Qs= qm • C + C • qm • qs + R • qm • qs + C • qs |
|
The slave latch |
State Transition Table
As evidenced by the Boolean expression we just derived, the master-slave flipflop has two state variables qm and qs and three input variables C, S, and R. As such, the flipflop has four states and eight different input conditions. We show the resulting state transition table below.
Given state
qmqs |
Input Condition
CSR |
| 000 |
001 |
010 |
011 |
100 |
101 |
110 |
111 |
| 00 |
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| 01 |
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| 10 |
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| 11 |
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Table 1
Our next step is to fill the table with the appropriate valuations of Qs and Qm in each cell. We do that by evaluating both Qs and Qm at the appropriate values of qmqs and CSR. For example, to fill the cell where qmqs = 10 and CSR = 000, we solve the Boolean expression and get
| Qm = S • C + R • qm + C • qm |
|
The master latch. |
| Qm = 0 • 0 + 0 • 1 + 0 • 1 |
|
|
| Qm = 0 • 0 + 1 • 1 + 1 • 1 |
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|
| Qm = 0 + 1 + 1 |
|
|
| Qm = 1 |
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|
| Qs= qm • C + C • qm • qs + R • qm • qs + C • qs
|
|
The slave latch. |
| Qs= 1 • 0 + 0 • 1 • 0 + 0 • 1 • 0 + 0 • 0 |
|
|
| Qs= 1 • 1 + 1 • 1 • 0 + 1 • 1 • 0 + 0 • 0 |
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|
| Qs= 1 + 0 + 0 + 0 |
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| Qs= 1 |
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|
Hence, we fill in the cell as shown in table 2 below.
Given state
qmqs |
Input Condition
CSR |
| 000 |
001 |
010 |
011 |
100 |
101 |
110 |
111 |
| 00 |
|
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| 01 |
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| 10 |
11 |
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| 11 |
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Table 2
We fill the rest of the table for you, as shown in Table 3 below. We welcome you to practice your evaluation skills by checking that our valuations are correct.
Given state
qmqs |
Input Condition
CSR |
| 000 |
001 |
010 |
011 |
100 |
101 |
110 |
111 |
| 00 |
00 |
00 |
00 |
00 |
00 |
00 |
10 |
10 |
| 01 |
00 |
00 |
00 |
00 |
01 |
01 |
11 |
11 |
| 10 |
11 |
11 |
11 |
11 |
10 |
00 |
10 |
10 |
| 11 |
11 |
11 |
11 |
11 |
11 |
01 |
11 |
11 |
Table 3
This is a pretty large table, so let’s observe a few facts. Notice that when the door to the master latch is closed (i.e. C = 0), the output of the slave latch is equal to the output of the master latch no matter what else may be going on – as we expected all along. Observe further that the outputs are driven by the given state of the master latch (qm) during that time. What this second piece of detail means is that once we close the door to the master latch, before the output of the slave latch gets a stable signal, the master will stabilize and settles into a definite voltage or current level. Furthermore, notice that when the door to the master latch is opened, the output of the slave latch is equal to the given state of the slave latch (Qs = qs). The meaning of this is that the output signal of the slave latch has settled down into a definite value. Again, this too we expected, and it is part of the reason a master-slave flipflop is so robust and reliable.
Just as we did with the table for the gated/clocked SR latch, we rewrite a condensed version of table 3 and show it below as table 4.
Given state
qmqs |
Input Condition
CSR |
| 0xx |
100 |
101 |
110 |
111 |
| 00 |
00 |
00 |
10 |
10 |
10 |
| 01 |
00 |
01 |
01 |
11 |
11 |
| 10 |
11 |
10 |
00 |
10 |
10 |
| 11 |
11 |
11 |
01 |
11 |
11 |
Table 4
The State Diagram
We now proceed to draw the state diagram from the information in table 4 (or table 3 if you want). As you will see below, a state diagram is just a picture that uses circles and arrows to show how the circuit moves between states. The Xs in the figure mean it does not matter if the cipher at that location is 0 or 1.
Figure 1
State Transitions Stability
Our final step is to clearly distinguish the stable state transitions from the unstable state transitions. In the state diagram the unstable state transitions are represent by the arrows that point from one circle to another. In the table, on the other hand, the unstable transitions are cells where QmQs is not equal to qmqs. In table 5 below we show the unstable transitions in green.
Given state
qmqs |
Input Condition
CSR |
| 0xx |
100 |
101 |
110 |
111 |
| 00 |
00 |
00 |
10 |
10 |
10 |
| 01 |
00 |
01 |
01 |
11 |
11 |
| 10 |
11 |
10 |
00 |
10 |
10 |
| 11 |
11 |
11 |
01 |
11 |
11 |
Table 5
