Introduction
A universal shift register is an integrated logic circuit that can transfer data in three different modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. For instance, on a particular job a universal register can load data in series (e.g. through a sequence of left shifts) and then transmit/output data in parallel.
Universal shift registers, as all other types of registers, are used in computers as memory elements. Although other types of memory devices are used for the efficient storage of very large volume of data, from a digital system perspective when we say computer memory we mean registers. In fact, all the operations in a digital system are performed on registers. Examples of such operations include multiplication, division, and data transfer.
In order for the universal shift register to operate in a specific mode, it must first select the mode. To accomplish mode selection the universal register uses a set of two selector switches, S1 and S0. As shown in Table 1, each permutation of the switches corresponds to a loading/input mode.
| Operating Mode | S1 | S0 |
| Locked |
0 |
0 |
| Shift-Right |
0 |
1 |
| Shift-Left |
1 |
0 |
| Parallel Loading |
1 |
1 |
Table 1
In the locked mode (S1S0 = 00) the register is not admitting any data; so that the content of the register is not affected by whatever is happening at the inputs. You may verify this detail by playing around with the main interactive circuit. For example, set L3L2L1L0 = 1010 and then cycle the clock to see that nothing changes at the outputs as long as S1S0 = 00. See Table 2.
| Clock Cycle |
L3 |
L2 |
L1 |
L0 |
|
Q3 |
Q2 |
Q1 |
Q0 |
| Initial Value |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
| Cycle 1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
Table 2
In the shift-right mode (S1S0 = 01) serial inputs are admitted from Q3 to Q0. You can confirm this aspect by setting the value of the shift-right switch according to the sequence 1100100 as you cycle the clock; see Table 3. Watch as the signals move from Q3 to Q0. In the shift-left mode (S1S0 = 10) the register works in a similar fashion, except that the signals move from Q0 to Q3.
| Clock Cycle |
Shift-Right Switch |
Q3 |
Q2 |
Q1 |
Q0 |
| Initial Value |
Initial Value |
0 |
0 |
0 |
0 |
| Cycle 1 |
1 |
1 |
0 |
0 |
0 |
| Cycle 2 |
1 |
1 |
1 |
0 |
0 |
| Cycle 3 |
0 |
0 |
1 |
1 |
0 |
| Cycle 4 |
0 |
0 |
0 |
1 |
1 |
| Cycle 5 |
1 |
1 |
0 |
0 |
1 |
| Cycle 6 |
0 |
0 |
1 |
0 |
0 |
| Cycle 7 |
0 |
0 |
0 |
1 |
0 |
Table 3
Finally, in the parallel loading mode (S1S0 = 11) data is read from the lines L0, L1, L2, and L3 simultaneously. Here, setting L3L2L1L0 = 1010 will cause Q3Q2Q1Q0 = 1010 after cycling the clock as depicted in Table 4.
| Clock Cycle |
L3 |
L2 |
L1 |
L0 |
|
Q3 |
Q2 |
Q1 |
Q0 |
| Initial Value |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
| Cycle 1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
Table 4
The universal shift register is able to operate in all these modes because of the four-to-one multiplexers that supply the flipflops. Our 4-bit universal shift register is built with four blocks each constituted of a 4X1 mux and a D-flipflop. All the blocks are essentially identical. Because all the multiplexers in the register are wired similarly, Figure 1 shows a representative multiplexer which we will reference in explaining the design of the universal register.
The L inputs come through port 11, which is why the L inputs are readable only when S1S0 = 11. The feedback Q wires are connected at port 00, so that when S1S0 = 00 the output Q of the D-flipflops feed back into the flipflops’ inputs resulting in no total change in the register content. Port 01 is wired to facilitate right-shifts. In mode S1S0 = 01 only port 01 is active and it takes its value from the previous more significant flipflop and passes it down to the flipflop wired to its mux output. Lastly port 10 is wired to conduce to left-shifts. Being the only active port when S1S0 = 10, it remits the output of the less significant flipflop sourcing into it to the flipflop wired to its mux output. As a consequence of this wiring pattern where each block of the register is an exact replica of any other block, the selector switches are able to align the behavior of all the multiplexers simultaneously. This coincidence of behavior is what we refer to as mode behavior of the universal register.
Figure 1: 4 to 1 Multiplexer
